• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A method for operating a current sense amplifier having a latch configuration improves the signal-to-noise ratio by setting the supply voltage for the latch configuration to be greater than a voltage which is present at the input of the current sense amplifier.
    公开号:US20010004334A1
    申请号:US09/742,133
    申请日:2000-12-20
    公开日:2001-06-21
    发明作者:Robert Feurle
    申请人:Infineon Technologies AG；
    IPC主号:G11C7-062
    专利说明:
    [0001] 1. Field of the Invention [0001]
    [0002] The invention relates to a method for operating a current sense amplifier having a latch configuration. A supply voltage is applied to the latch configuration. Transistors of the latch configuration are connected to one another via nodes and are connected to precharge transistors. The current sense amplifier has sense transistors which are connected downstream of an input and are provided between the latch configuration and an output stage. The precharge transistors are provided between the input and the supply voltage and are controlled via the nodes. [0002]
    [0003] Such a current sense amplifier is conventional and has been in widespread use for a long time. The signal-to-noise ratio of such a current sense amplifier is in many cases still unsatisfactory which can be attributed to technological problems during the production of the current sense amplifier. [0003]
    [0004] Specifically, as a result of technological process fluctuations, the nodes in the current sense amplifier may have different capacitances. This means that the nodes can discharge themselves even when identical voltages are present at them. This parasitic discharging process is dependent on the gate voltage applied to the sense transistors. In other words, there are voltage ranges in which the signal-to-noise ratio of the current sense amplifier drifts into unsatisfactory ranges. [0004]
    [0005] In order to overcome these difficulties, a relatively long waiting time has been used in the past to ensure that the signals applied to the gates of the sense transistors have been built up or developed sufficiently before actually switching the current sense amplifier on. It has also been suggested to use slower operating sense concepts. However, these approaches have been found to be cumbersome. [0005] SUMMARY OF THE INVENTION
    [0006] It is accordingly an object of the invention to provide a method for operating a current sense amplifier configuration which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and which improves the signal-to-noise ratio in a simple manner. With the foregoing and other objects in view there is provided, in accordance with the invention, a method for operating a current sense amplifier configuration, the method includes the steps of: providing a current sense amplifier having an input, a latch configuration, precharge transistors, sense transistors, and an output stage, the latch configuration having transistors connected to one another via nodes and connected to the precharge transistors, the sense transistors being connected downstream of the input and being connected between the latch configuration and the output stage, the precharge transistors being controlled via the nodes and being connected between the input and a supply voltage; [0006]
    [0007] providing the supply voltage to the latch configuration; and [0007]
    [0008] providing a given voltage at the input, the given voltage having a value at most equal to a difference between the supply voltage and a threshold voltage or switch-on voltage of p-channel MOS transistors of the latch configuration. [0008]
    [0009] In other words, the object of the invention is achieved by setting the voltage which is present at the input to be lower than the supply voltage. [0009]
    [0010] Thus, in the method according to the invention, the voltage which is applied to the gates of the sense transistors is never greater than the supply voltage for the latch configuration. The voltage which is present at the input is, optimally, not greater than the difference between the supply voltage and the threshold voltage of p-channel transistors in the latch configuration. [0010]
    [0011] The method according to the invention thus allows a selection of the optimum voltages for supplying the latch configuration and the input of the sense transistors, so that a sense process can be carried out extremely quickly. [0011]
    [0012] The voltage which is present at the input and the supply voltage for the latch configuration can advantageously be set separately from one another. [0012]
    [0013] Other features which are considered as characteristic for the invention are set forth in the appended claims. [0013]
    [0014] Although the invention is illustrated and described herein as embodied in a method for operating a current sense amplifier, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. [0014] BRIEF DESCRIPTION OF THE DRAWING
    [0015] The single figure is a circuit diagram of a current sense amplifier used for the method according to the invention. [0015] DESCRIPTION OF THE PREFERRED EMBODIMENT
    [0016] Referring now to the single figure of the drawing in detail, there is shown a current sense amplifier having a normal latch configuration with p-channel MOS transistors P[0016] 0 and P1, and n-channel MOS transistors N0, N1. The gate of the p-channel MOS transistor P0 is connected firstly via a node A1 to the gate of the n-channel MOS transistor N0, and to the source-drain path of the transistors P1 and N1. In a similar way, the gate of the p-channel MOS transistor P1 is connected firstly via a node A2 to the gate of the n-channel MOS transistor N1, and secondly to the source-drain path of the transistors P0 and N0.
    [0017] A p-channel MOS precharge transistor P[0017] 3 is connected in parallel with the p-channel MOS transistor P1, and a p-channel MOS precharge transistor P2 is provided in parallel with the p-channel MOS transistor P0. The gates of the transistors P2 and P3 are connected to a sense node SENSE.
    [0018] The latch configuration has a connection C to which a supply voltage VBB is applied. The p-channel MOS transistors P[0018] 4 and P5, respectively, are connected between one input MDQ or bMDQ, respectively, of the current sense amplifier and the connection C, and their gates are connected to the node A1 or the node A2, respectively. The respective inputs MDQ and bMDQ are, furthermore, respectively connected to gates of n-channel MOS sense transistors N3 and N2, respectively, which are connected in series with the source-drain paths of the transistors P1, N1 (cf. transistor N3 with the node B1) or of the transistors P0 and N0 (cf. transistor N2 with the node B2), respectively. The transistors N2 and N3 are connected via a node M to an n-channel MOS transistor N4, whose gate is connected to the node SENSE.
    [0019] The node SENSE is connected via an inverter I and a delay element D to an output DQRST. [0019]
    [0020] The above configuration of the current sense amplifier is conventional. [0020]
    [0021] As has already been explained in the introduction, process fluctuations during the production of the current sense amplifier can, for example, result in different capacitances being present at the nodes A[0021] 1 and A2. This means that the nodes A1 and A2 can discharge themselves even when identical voltages are present on the sense transistors N2 and N3. This parasitic discharge process is in this case dependent on the gate voltage applied to the sense transistors N2 and N3, that is to say it is dependent on the voltage applied to the input MDQ and the input bMDQ, respectively.
    [0022] In order now to keep this initial discharging of the nodes A[0022] 1 and A2 as small as possible, the voltage which is applied to the respective input MDQ or bMDQ must not be greater than the supply voltage VBB at the connection C of the latch configuration. Specifically, if this condition is satisfied, this prevents the nodes A1 and A2 from discharging even if the capacitances of these nodes are different, since the leakage currents are minimized.
    [0023] Optimum voltage conditions are present when the voltage applied to the respective input MDQ or bMDQ is not greater than the difference between the supply voltage VBB at the connection C of the latch configuration and the threshold voltage of the p-channel MOS transistors P[0023] 0 and P1 in the latch configuration.
    [0024] By selecting the optimum voltages for the supply for the latch configuration and the respective input MDQ or bMDQ of the sense transistors N[0024] 3 or N2, respectively it is possible to have a sense process that takes place extremely quickly. The voltages at the respective input MDQ or bMDQ and the supply voltage VBB at the connection C can advantageously also be set separately from one another.
    权利要求:
    Claims (2)
    [1" id="US-20010004334-A1-CLM-00001] 1. A method for operating a current sense amplifier configuration, the method which comprises:
    providing a current sense amplifier having an input, a latch configuration, precharge transistors, sense transistors, and an output stage, the latch configuration having transistors connected to one another via nodes and connected to the precharge transistors, the sense transistors being connected downstream of the input and being connected between the latch configuration and the output stage, the precharge transistors being controlled via the nodes and being connected between the input and a supply voltage;
    providing the supply voltage to the latch configuration; and
    providing a given voltage at the input, the given voltage having a value at most equal to a difference between the supply voltage and a threshold voltage of p-channel MOS transistors of the latch configuration.
    [2" id="US-20010004334-A1-CLM-00002] 2. The method according to
    claim 1 , which comprises setting the supply voltage and the given voltage independently of one another.
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    同族专利:
    公开号 | 公开日
    DE19961518B4|2007-03-29|
    US6317374B2|2001-11-13|
    DE19961518A1|2001-07-05|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20030210078A1|2002-05-08|2003-11-13|University Of Southern California|Current source evaluation sense-amplifier|US5257236A|1991-08-01|1993-10-26|Silicon Engineering, Inc.|Static RAM|
    US5502680A|1995-02-16|1996-03-26|Cirrus Logic Inc|Sense amplifier with pull-up circuit for accelerated latching of logic level output data|
    US5615161A|1996-02-22|1997-03-25|Hal Computer Systems, Inc.|Clocked sense amplifier with positive source feedback|
    KR100189750B1|1996-07-29|1999-06-01|구본준|Latch-type sensing amplification part having negative feedback means|
    US6002626A|1997-08-01|1999-12-14|International Business Machines Corporation|Method and apparatus for memory cell array boost amplifier|US6466501B2|2000-06-28|2002-10-15|Hynix Semiconductor Inc.|Semiconductor memory device having sense amplifier and method for driving sense amplifier|
    DE10219649C1|2002-05-02|2003-11-27|Infineon Technologies Ag|Differential current evaluation circuit and sense amplifier circuit for evaluating a memory state of an SRAM semiconductor memory cell|
    US7263016B1|2004-06-07|2007-08-28|Virage Logic Corporation|Method and system for pre-charging and biasing a latch-type sense amplifier|
    US7221605B2|2004-08-31|2007-05-22|Micron Technology, Inc.|Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets|
    US7176719B2|2004-08-31|2007-02-13|Micron Technology, Inc.|Capacitively-coupled level restore circuits for low voltage swing logic circuits|
    US7236415B2|2004-09-01|2007-06-26|Micron Technology, Inc.|Sample and hold memory sense amplifier|
    US7298180B2|2005-11-17|2007-11-20|Taiwan Semiconductor Manufacturing Co., Ltd.|Latch type sense amplifier|
    KR100864626B1|2007-04-02|2008-10-22|주식회사 하이닉스반도체|Semiconductor memory device and operation method thereof|
    US9250271B2|2013-08-26|2016-02-02|Globalfoundries Inc.|Charge pump generator with direct voltage sensor|
    法律状态:
    2001-09-24| AS| Assignment|Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FEURLE, ROBERT;REEL/FRAME:012190/0464 Effective date: 20010122 |
    2001-10-25| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2005-05-09| FPAY| Fee payment|Year of fee payment: 4 |
    2009-05-07| FPAY| Fee payment|Year of fee payment: 8 |
    2010-01-13| AS| Assignment|Owner name: QIMONDA AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:023828/0001 Effective date: 20060425 |
    2013-02-22| FPAY| Fee payment|Year of fee payment: 12 |
    2015-05-08| AS| Assignment|Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001 Effective date: 20141009 |
    2015-09-03| AS| Assignment|Owner name: POLARIS INNOVATIONS LIMITED, IRELAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES AG;REEL/FRAME:036539/0196 Effective date: 20150708 |
    优先权:
    申请号 | 申请日 | 专利标题
    DE19961518.7||1999-12-20||
    DE19961518||1999-12-20||
    DE19961518A|DE19961518B4|1999-12-20|1999-12-20|Method for operating a current sense amplifier|
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